Fall 2006 NACSA Job Fair Seminar

Seminar: The IC Nanometer Concerns
Challenges and Trends of IC Designs at 65nm and Beyond

Designing ICs in the nanometer age is a high-stakes race. Is it true that few companies can afford to compete in -- and even fewer can win? Hear the perspectives from senior technologists from the world's top semiconductor and EDA companies. Will mask costs and the impact of process variability force chip designers to stay with older process technologies, or will there be transparent tools and methodologies to scale designs in a new process technology? Will ballooning capital equipment expenses delay new capacity or price out design rules for mainstream applications? And which design-for-manufacturing (DFM) technologies, or other critical design solutions, delivered when, will be critical for the chip design companies?

The senior technologists from some of the leading companies in the semiconductor industry, will discuss and debate how they think the overall industry will successfully transition to the nanometer age. Specific examples from the technologists' broad exposure to industry trends will help illustrate their opinions and predictions.

NACSA invites its members and other semiconductor professionals with interests in IC designs to join us in this interesting event.

Date & Time: Saturday, Sept. 30, 2006
Location: Hyatt Regency Santa Clara, 5101 Great America Pkwy, Santa Clara, CA 95054

Agenda:

• 3:30 PM ~ 3:45 PM: Moderator Introduction
  • Jim Hogan, Chairman, Ponte Solutions
• 3:45 PM ~ 4:30 PM: Presentation by Guest Speakers
  • Vassilios Gerousis, Technologist, Cadence Design Systems
  • Atul Sharan, President & CEO, Clear Shape Technologies
  • Hua-yu Liu, VP of Product Marketing, Brion Technologies
  • Srinivas Raghvendra, Senior Director of DFM Solutions, Synopsys
  • David Lan, Senior Manager of Design Methodology, TSMC
• 4:30 PM ~ 5:30 PM: Q/A